Cda4205 Computer Architecture Exam 2

Front 1

Data Path

Back 1

Elements that process data and addresses in the CPU

 Registers, ALUs, mux’s, memories, …

Front 2

Critical Path

Back 2

The longest propagation sequence through the datapath. It determines how quickly you can do the next operation.
Typically it is something like load (lw) being the longest so we use the data path of lw.

Front 3

Pipelining

Back 3

is an implementation technique in which multiple instructions are overlapped in execution.

Five stages, one step per stage1. IF: Instruction fetch from memory2. ID: Instruction decode & register read3. EX: Execute operation or calculate address4. MEM: Access memory operand5. WB: Write result back to register

Front 4

Pipeline Hazard

Back 4

There are situations in pipelining when the next instruction cannot execute in thefollowing clock cycle. These events are called hazards, and there are three differenttypes.

Structural, Data and Control

Front 5

Data Hazard

Back 5

Need to wait for previous instruction tocomplete its data read/write

Data hazards occur when the pipeline must be stalled because one step must waitfor another to complete.

In a computer pipeline, data hazards arise from the dependence of oneinstruction on an earlier one that is still in the pipeline

Suppose you found a sock at the folding station for whichno match existed. One possible strategy is to run down to your room and searchthrough your clothes bureau to see if you can find the match. Obviously, while youare doing the search, loads must wait that have completed drying and are ready tofold as well as those that have finished washing and are ready to dry.

Front 6

Control Hazard/ Branch Hazard

Back 6

Deciding on control action depends onprevious instruction

When the properinstruction cannotexecute in the properpipeline clock cyclebecause the instructionthat was fetched is not theone that is needed; thatis, the fl ow of instructionaddresses is not what thepipeline expected.

Front 7

Structural Hazard

Back 7

A required resource is busy

It means that the hardware cannotsupport the combination of instructions that we want to execute in the same clockcycle.

A structural hazard in the laundry room would occur if we used a washer/`dryercombination instead of a separate washer and dryer, or if our roommate wasbusy doing something else and wouldn’t put clothes away. Our carefully scheduledpipeline plans would then be foiled.

Front 8

Load-use Data Hazard

Back 8

A specific form of datahazard in which the databeing loaded by a loadinstruction has not yetbecome available whenit is needed by anotherinstruction.

Front 9

Branch Penalty

Back 9

 Based on typical branch behavior

 Example: loop and if-statement branches

 Predict backward branches taken

 Predict forward branches not taken

Front 10

Branch Prediction

Back 10

A method of resolving a branch hazard that assumes a given outcome for the branch and proceeds from that assumption rather than waiting to ascertain the actual outcome.

Front 11

Static and Dynamic Branch Prediction

Back 11

Prediction ofbranches at runtime usingruntimeinformation.

Front 12

Data Forwarding

Back 12

Also called by passing. A method of resolving a data hazard by retrieving the missing data element from internal buffers rather than waiting for it to arrive from programmer visible registers or memory.

Front 13

Pipeline Stall

Back 13

Also called bubble. A stall initiated in order to resolve a hazard.