Winter 2016 Plc Final Exam

Front 1

you can place two or more input instructions in series in a PLC ladder logic rung

Back 1

True

Front 2

You can place tow or more output instructions in parallel in a PLC ladder logic rung

Back 2

True

Front 3

In a PLC ladder logic rung, the last instruction must be an input instruction

Back 3

False

Front 4

input address instructions may be used two or more times in a PLC ladder logic diagram

Back 4

True

Front 5

The output address instructions may be used two or more times in a PLC ladder logic diagram

Back 5

False

Front 6

XIC is an acronym for

Back 6

examine if closed

Front 7

XIO is an acronym for

Back 7

Examine if open

Front 8

an Allen Bradley SLC 500 series PLC has _________ words addressed from N7:) to N7:255

Back 8

256

Front 9

An Allen Bradley SLC 500 series PLC has __________ address from t4:0 to t4:255

Back 9

256

Front 10

An Allen Bradley SLC 500 series PLC has __________ address from c5:0 to c5:255

Back 10

256

Front 11

in order to change the program, the PLC must be in ____________ mode

Back 11

offline

Front 12

A method of testing the PLC system without actually closing or opening input devices is to test PLC in the __________ mode

Back 12

force

Front 13

PLC program execution, or program _____________ flows from left to right on each rung, starting from the top ring and continuing to the bottom rung

Back 13

Scan

Front 14

A ______ timer has present value timer instructions

Back 14

fixed

Front 15

the ______ format uses coils to display the timer instructions

Back 15

coil

Front 16

the ___________ format uses a box shape to display the timer instruction

Back 16

Block

Front 17

The content of the ________ register is the preset value that the timer is initialized to hold

Back 17

present

Front 18

The time that the timer has been timing is held in the _________ register

Back 18

accumulated

Front 19

you must use the (RES) instruction to reset a retentive timer ON-delay instruction

Back 19

True

Front 20

You must energize an on-delay timer instruction to start it

Back 20

true

Front 21

addresses t4:0 through t4:255 are used for timer instructions

Back 21

True

Front 22

Timer instructions in fixed SLC 500 PLC systems have variable time base values

Back 22

True

Front 23

You can reset an on delay-retentive timer by de-energizing it

Back 23

false

Front 24

when the timer ON-delay instruction t4:0 is timing, its normally closed timer contact (T4:0/TT) is closed

Back 24

False

Front 25

You must de-energize an OFF-delay timer instriction to start it

Back 25

True

Front 26

When the timer OFF-delay instruction T4:0 is timming; its normally closed timer timing contact (T4:0/TT) is closed

Back 26

True

Front 27

the timer OFF-delay instruction is a retentive timer instruction

Back 27

False

Front 28

When the ON-Delay timer instruction T4:0 is finished timing, its timer timing coil (T4:0/TT) is

Back 28

de-energized

Front 29

When the ON-delay timer instruction T4:0 is finished timing, its timer done coil (T4:0/DN) is

Back 29

energized

Front 30

When the non-retentive ON-Delay timer instruction T4:0 is ___________ its accumulated register will reset its content

Back 30

disablede

Front 31

When the _______ timer is de-energized, content of its accumulated register will reset to zero

Back 31

TON

Front 32

the _______ instruction transfers either a number or content of a register to a destination register

Back 32

MOV

Front 33

You must use the _______ instruction to reset a non-retentive timer instruction

Back 33

RES

Front 34

timer T4:0 has a time base 0.01 and a preset of 500. how many seconds?

Back 34

5 sec, answer on test "none of the above"

Front 35

Internal bit c5:0/CU is on when the input to the count up instruction c5:0 is open

Back 35

false

Front 36

there are two types of PLC counter instructions

Back 36

True

Front 37

The content of an accumulated register in the count down instruction decrements whenever there is a low-to-high counter input switch transition

Back 37

true

Front 38

the accumulated register for counter instruction c5:0 is addressed as c5::0.acc

Back 38

true

Front 39

the counter up instruction c5:0 in a fixed SLC 500 PLC uses two sixteen bit registers

Back 39

False

Front 40

the counter done bit for the counter instruction c5:1 is addressed as c5:1/dn

Back 40

false

Front 41

the counter of an accumulated register in the count up instruction increments whenever there is a lot to high counter input switch transition

Back 41

True

Front 42

Internal bit c5:0/CD is on the nput to the count up instruction c5:0 is closed

Back 42

False

Front 43

internal bit c5:0/dn is on when the input to the count upo instruction c5:0 is closed

Back 43

True

Front 44

internal bit c5:0/cu is on when the input to the count up instruction c5:0 is open

Back 44

False

Front 45

the count up instruction c5:0 in a fixed SLC 500 PLC uses two sixteen bit registers

Back 45

False

Front 46

The accumulated register for counter instruction c5:0 is addressed as c5:0.acc

Back 46

true

Front 47

there are three types of PLC counter instructions: RTO, CTU, CTD

Back 47

False

Front 48

When an input instruction to the count down instruction c5:0 is closed, the done bit energizes

Back 48

False

Front 49

Each counter accunulateor can hold a maximum positive number of +32,768

Back 49

False

Front 50

When the content of the count up register c5:0.pre and c5:0.acc are equal, the _________ coil energizes

Back 50

done

Front 51

Done files _______ through _________ can be used for counter instruction

Back 51

c5:0 - c5:255

Front 52

You must use the _______ instruction to reset a count down instruction

Back 52

reset

Front 53

The accumulated value for counter instruction c5:0 is in the _______ register

Back 53

accumulated

Front 54

you must energize a JMP coil to activate the JMP instruction

Back 54

True

Front 55

You must energize a MCR coil to activate the MCR instruction

Back 55

false

Front 56

the states of the instructions that are jumped over change

Back 56

False

Front 57

When the MCR instruction is de-energized, the state of the instructions that are between the MCR instructions remain the same

Back 57

False

Front 58

In a GEQ instruction, when source A is less then Source B, the current can flow through the GEQ instruction block

Back 58

False

Front 59

In a GEQ instruction, when Source A is greater than Source B, the current can flow through the GEQ instruction block

Back 59

True

Front 60

Two compare instructions cannot be connected in series

Back 60

False

Front 61

in a GRT instruction, Source A and Source B can both be numbers

Back 61

False

Front 62

When a rung is skipped over, the state of its I/O instructions remains the same

Back 62

True