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3 Cards in this Set
- Front
- Back
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Explain the operation of a Serial In Serial Out Register |
A serial signal is input into the first D type latch. As new data is input, the clock is triggered and moves all the data one latch to the right. To get an output, the clock needs to be triggered until all the data has moved along the latches into the output line. This however means the data is not retained |
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Explain the operation of a Parallel In Parallel Out Register |
The bit pattern is transferred into the Register when the load line is high. Data is read out from the Register when the output enable line is set where the data appears at the output of the tri state buffers. |
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Explain the operation of a Serial In Parallel Out Register |
Data is read out via the tri state buffers by the output enable line and is clocked synchronously by the clock signal. It is also important to note that the clock is disabled by the output enable line to prevent the outputs of the flip flops changing while data is being read out. |
