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72 Cards in this Set
- Front
- Back
Response time / Execution Time
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A user measurement - The time between the start and completion of a task including dis accesses, memory accesses, IO activities, operating system overhead, CPU execution time and so on
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Throughput/bandwidth
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Number of tasks completed per unit of time
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CPU Execution time / CPU time
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The actual time the CPU spends computing for a specific task
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user CPU time
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The CPU time spent in a program itself
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system CPU time
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The CPU time spent in the operating system performing tasks on behalf of the program
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Clock Cycle / Cycle/ Tick/ Period
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The time for one clock period, usually of the processor clock, which runs at a constant rate
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Clock period
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The length of each clock cycle
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Clock rate
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Inverse of the clock period. GHz
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CPU Exeuction time for a program (Equation)
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= CPU clock cycles for a program / Clock rate
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CPU Clock cycles (equation)
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= instructions for a program X average clock cycles per instruction
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CLock cycles per instruction (CPI)
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average number of clock cycles per instruction for a program or program fragment
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Instruction count
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The number of instructions executed by the program
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CPU Time (equation) (2)
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= (Instruction Count X CPI) / Clock Rate
OR = Instruction Count X CPI X Clock cycle time |
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Time (Equation)
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= (Instructions / Program) X (Clock cycles / Instruction) X (Seconds / Clock Cycle)
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Desktop Computer
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A general purpose computer owned by an individual or a small
group. Often used for word processing, video games, etc |
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Server
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A general purpose computer that is accessed by many people via
a computer network. Large companies may use servers to support e-commerce websites or enterprise-wide services. Small companies may use servers for simpler tasks |
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Supercomputers
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Servers used to support high-end scientific and engineering
applications, e.g., molecular-scale simulation |
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Embedded computers (processors
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A computer inside another device used for running one
predetermined application |
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Five classic components of a computer
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input, output,
memory, datapath, and control |
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datapath + control = ?
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processor
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Moore's law
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The number of transistors on a single chip will double every two years
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What has happened with
1.) Processor Performance 2.) Power Density 3.) Clock rates |
1.) Increased
2.) Increased 3.) Hit a wall and started to decrease (why?) -Too much power consumption/heat |
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What is the only option for sustained performance growth?
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More cores on chip
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ALU
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Arithmetic Logic Unit
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Register File
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Where the ALU reads its input from and writes its output to
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Pipelining
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Technique to efficiently organize instructions sent to the ALU
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As we move to many cores how do we get instructions and data to the processor? (2)
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Big wire that goes to each core, multiple wires for each core
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Memory Structure
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The physical places were data and
instructions are stored. Can be organized in many ways. The most common organization is hierarchical |
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Memory Hardware
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Different properties of the hardware that affect the use and structure
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Resource consumption
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the number of units of a resource
used to complete task (clock cycles) |
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What are the only two ways to increase performance
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1.) Reduce length of the clock cycle
2.) reduce the number of clock cycles needed to run the program |
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Benchmarks
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Set of programs that measure performance
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Micro-Benchmarks
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Test a particular component of a system
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Macro-Benchmarks
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Test the whole system on real world simulations of data
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Principles of Machine Design (2)
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1.) Instructions are represented as numbers and are indistinguishable from data
2.) Programs are stored in alterable memory just like data |
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Cisc
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Complex Instruction Set Architecture
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Risc
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Reduced Instruction Set Architecture
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Risc Vs Cisc
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Cisc Has instructions that take multiple clock cycles while in Risc each instruction only takes 1 clock cycle so pipelining is possible.
Cisc requires less memory to store instructions than risc Cisc has emphasis on hardware while risc has emphasis on software |
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What are the three instruction types in MIPS
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R, I, J
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Risc Design Principles (4)
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1.) Simplicity Favors regularity
2.) Smaller is faster 3.) Make the common case fast 4.) Good demand requires good compromise |
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Alignment Restriction
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the memory address of a word must be
on natural word boundaries |
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Big Endian
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Lowest address is the most significant
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Little Endian
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Lowest address is the least significant
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What does a logical shift mean
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fill with zeros
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data race
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Two memory accesses from different threads to the same
location, and at least one is a writ |
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Atomic Exchange
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interchanges a value
in a register for a value in memory atomically, i.e., as one operation |
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activation record
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The segment of the stack
containing a procedure’s saved registers and local variables |
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heap
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Dynamic data segment
(aka heap) for structures that grow and shrink |
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Combinational logig
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Output depends on current value of inputs
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Sequential function
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output depnds on current input and some internal states
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SR latch truth table
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S R Action
0 0 No Change 0 1 Q = 0 1 0 Q = 1 1 1 Restricted |
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Order of how memory was designed
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SR latch, D Latch, D Flip Flop
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D flip flop truth table
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Clock D Q Qprev
Rising 0 0 X Rising 1 1 X Non-Ri X Qprev |
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set-up time
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is the minimum time the D signal must be stable before the C signal falling edge
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hold time
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is the minimum time the D signal must be stable after C signal falling edge.
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Three state d-latch
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Adds enable signal that determines when the latch is for writing or reading
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SRAM
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static ram
large memory built on flip flops. Piece together decoders instead of one large one. Memory lost when power lost |
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DRAM
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Value stored in capacitors but capacitors can leak. and as transistors and capacitors get smaller, leaking rate stays the same.
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Flash Memory
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Floating gate and control gate, word selector and bit line. Read bit line.
Writing a 0 requires Hot electron injection Writing a 1 requires Quantum tunneling |
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Flash Memory advantages/disadvantages
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Advantages:
Lasts a long time and no power consumption when idle disadvantages: not byte addressable eventually can't write anymore because of tunneling |
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PCRam
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Phase Change RAM
Uses chalconide glass that is heated or cooled and has different states Benefits: ● Very fast reads and writes, though writes take longer ● Under stable temperatures, memory storage is permanent ● Write to individual words ● Highly scalable ● Negatives: ● Write limited (10^9 vs 10^5 for flash) ● Sensitive to temperature fluctuation |
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What functions will our ALU perform (6)
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Add
Sub SLT Nor Or And |
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Ripple Adder
And Carry Look Ahead |
Ripple is sequential, carry out from one goes to carry in of another
Look ahead calculates carrys for all |
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How do we implement twos complement subtractor
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Make carry in 1 for first adder and flip all the b bits. Binvert line
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when does twos complement overflow happen
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1.) Sum of two positives is negative
2.) Sum of two negatives is positve |
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How does mips handle overflow
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interrupt
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What comprises around 40% of computing time and can be only done _______
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Data management / serially
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What does Amdahls law state
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-Effort spent on parallel processing is useless instead of also increasing serial processing power
-‘law’ dictates how the maximum speedup of a program depends on the amount of that program requiring serial execution. |
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What is Amdahls Law (equation)
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1 / (S + P/N)
Where S is non parallelizable part P is parallizable part N is number of processors |
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What is the problem with parallel processing on many cores according to Amdahls law
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Always levels out the amount of speedup we can get
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Problems with Amdahls Law
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1.) Assumes P and N are independent
2.) the problem size increases with the number of processors and the run time stays constant! |
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Generally what does Guastak;ljsad's law say
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Problems with Amdahls law have been overcome
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