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62 Cards in this Set
- Front
- Back
you can place two or more input instructions in series in a PLC ladder logic rung |
True |
|
You can place tow or more output instructions in parallel in a PLC ladder logic rung |
True |
|
In a PLC ladder logic rung, the last instruction must be an input instruction |
False |
|
input address instructions may be used two or more times in a PLC ladder logic diagram |
True |
|
The output address instructions may be used two or more times in a PLC ladder logic diagram |
False |
|
XIC is an acronym for |
examine if closed |
|
XIO is an acronym for |
Examine if open |
|
an Allen Bradley SLC 500 series PLC has _________ words addressed from N7:) to N7:255 |
256 |
|
An Allen Bradley SLC 500 series PLC has __________ address from t4:0 to t4:255 |
256 |
|
An Allen Bradley SLC 500 series PLC has __________ address from c5:0 to c5:255 |
256 |
|
in order to change the program, the PLC must be in ____________ mode |
offline |
|
A method of testing the PLC system without actually closing or opening input devices is to test PLC in the __________ mode |
force |
|
PLC program execution, or program _____________ flows from left to right on each rung, starting from the top ring and continuing to the bottom rung |
Scan |
|
A ______ timer has present value timer instructions |
fixed |
|
the ______ format uses coils to display the timer instructions |
coil |
|
the ___________ format uses a box shape to display the timer instruction |
Block |
|
The content of the ________ register is the preset value that the timer is initialized to hold |
present |
|
The time that the timer has been timing is held in the _________ register |
accumulated |
|
you must use the (RES) instruction to reset a retentive timer ON-delay instruction |
True |
|
You must energize an on-delay timer instruction to start it |
true |
|
addresses t4:0 through t4:255 are used for timer instructions |
True |
|
Timer instructions in fixed SLC 500 PLC systems have variable time base values |
True |
|
You can reset an on delay-retentive timer by de-energizing it |
false |
|
when the timer ON-delay instruction t4:0 is timing, its normally closed timer contact (T4:0/TT) is closed |
False |
|
You must de-energize an OFF-delay timer instriction to start it |
True |
|
When the timer OFF-delay instruction T4:0 is timming; its normally closed timer timing contact (T4:0/TT) is closed |
True |
|
the timer OFF-delay instruction is a retentive timer instruction |
False |
|
When the ON-Delay timer instruction T4:0 is finished timing, its timer timing coil (T4:0/TT) is |
de-energized |
|
When the ON-delay timer instruction T4:0 is finished timing, its timer done coil (T4:0/DN) is |
energized |
|
When the non-retentive ON-Delay timer instruction T4:0 is ___________ its accumulated register will reset its content |
disablede |
|
When the _______ timer is de-energized, content of its accumulated register will reset to zero |
TON |
|
the _______ instruction transfers either a number or content of a register to a destination register |
MOV |
|
You must use the _______ instruction to reset a non-retentive timer instruction |
RES |
|
timer T4:0 has a time base 0.01 and a preset of 500. how many seconds? |
5 sec, answer on test "none of the above" |
|
Internal bit c5:0/CU is on when the input to the count up instruction c5:0 is open
|
false |
|
there are two types of PLC counter instructions |
True |
|
The content of an accumulated register in the count down instruction decrements whenever there is a low-to-high counter input switch transition |
true |
|
the accumulated register for counter instruction c5:0 is addressed as c5::0.acc |
true |
|
the counter up instruction c5:0 in a fixed SLC 500 PLC uses two sixteen bit registers |
False |
|
the counter done bit for the counter instruction c5:1 is addressed as c5:1/dn |
false |
|
the counter of an accumulated register in the count up instruction increments whenever there is a lot to high counter input switch transition |
True |
|
Internal bit c5:0/CD is on the nput to the count up instruction c5:0 is closed |
False |
|
internal bit c5:0/dn is on when the input to the count upo instruction c5:0 is closed |
True |
|
internal bit c5:0/cu is on when the input to the count up instruction c5:0 is open |
False |
|
the count up instruction c5:0 in a fixed SLC 500 PLC uses two sixteen bit registers |
False |
|
The accumulated register for counter instruction c5:0 is addressed as c5:0.acc |
true |
|
there are three types of PLC counter instructions: RTO, CTU, CTD |
False
|
|
When an input instruction to the count down instruction c5:0 is closed, the done bit energizes |
False |
|
Each counter accunulateor can hold a maximum positive number of +32,768 |
False |
|
When the content of the count up register c5:0.pre and c5:0.acc are equal, the _________ coil energizes |
done |
|
Done files _______ through _________ can be used for counter instruction |
c5:0 - c5:255 |
|
You must use the _______ instruction to reset a count down instruction |
reset |
|
The accumulated value for counter instruction c5:0 is in the _______ register |
accumulated |
|
you must energize a JMP coil to activate the JMP instruction |
True |
|
You must energize a MCR coil to activate the MCR instruction |
false |
|
the states of the instructions that are jumped over change |
False |
|
When the MCR instruction is de-energized, the state of the instructions that are between the MCR instructions remain the same |
False |
|
In a GEQ instruction, when source A is less then Source B, the current can flow through the GEQ instruction block |
False |
|
In a GEQ instruction, when Source A is greater than Source B, the current can flow through the GEQ instruction block |
True |
|
Two compare instructions cannot be connected in series |
False |
|
in a GRT instruction, Source A and Source B can both be numbers |
False |
|
When a rung is skipped over, the state of its I/O instructions remains the same |
True |