II. DERIVATION OF THE CONVERTER STRUCTURE
The new generated topology is called Full-Bridge Hybrid Switched Capacitor (FBHSC) Inverter. A Half-Bridge version was previously presented [30]. The new topology was generated initially by differential connection [31]–[33] between two HSC dc-dc converter [16] (cf. Fig. 2a), which was generated as a bidirectional version of the HSC boost dc-dc converter [34], [35]. The unidirectional dc-dc version can be seen as an integration between a conventional boost dc-dc converter and a voltage multiplier circuit [36].
Some known characteristics of a dc-dc converter are necessary to ensure the generation of a dc-ac converter through differential connection. The HSC dc-dc converter, used as building cell, has all these characteristics, which are:
1) Topology must have voltage source characteristic on the input (i.e. buck-type); 2) Topology must have current source characteristic on the output (i.e. boost-type); 3) Topology must be bidirectional, in order to process both positive and negative current in the output; 4) Topology must have the capability of synthesize an ac output voltage with a dc offset. Fig. 2 presents all steps to generate the proposed topology from the HSC dc-dc converter. The main building cell is presented in Fig. 2a. In Figs. 2b and 2c, two dc-dc converter are connected through a differential connection. Fig. 2d shows the connection between midpoints of each leg, in order to reduce the number of capacitors. Finally, Fig. 2e presented the proposed topology. As previously showed in [37], [38], the same procedure applied can generate a conventional Full- Bridge Inverter from a bidirectional dc-dc buck converter. III. THEORETICAL ANALYSIS OF THE PROPOSED CONVERTER In order to clarify the theoretical analysis, it is necessary to define the proposed topology nomenclature. Capacitors with even index will be called floating capacitors, which are unique to each converter’s leg. The link capacitors have odd index and they are common for all inverter legs. The link capacitor C3 on Fig. 1 is ‘implicit’ because this capacitor is redundant to the theoretical analysis (i.e. its effect can be represented by an equivalent capacitor connected in parallel to C1). Nevertheless, in the prototype all link capacitors must be connected The proposed topology can operate such as common inverters, processing active or reactive power, which will depend on the load angle φ. Initially the load will be assumed as a sinusoidal current source iab, with a function defined by where θ = ω t, and ω is the angular output frequency. Regarding the switches, in each leg all devices with even index have the same modulation signal, same as the devices with odd index. However, each switch must have his own gate driver circuit, as the Neutral Point Clamped Inverter (NPC) or the Floating Capacitor (FC) Inverters, although some alternative topologies of gate-driver circuits could be employed to reduce the number of components [39], [40]. In order to avoid short-circuit in the capacitors, gating signal must be complementary with a dead time between even and odd switches. Then, even switches of leg ‘a’ will be gated by the switching function sa (and 1 − sa to the odd switches), and in the leg ‘b’, even switches will be gated by the switching function …show more content…
Both unipolar and bipolar PWM [41] can be employed. FBHSC modulation scheme is the same as the conventional FB inverter, only with addition of the modulation signal to additional switches.
The proposed topology has only four conduction states, which are presented in Fig. 3.
MOSFET on-resistance Ron is necessary to limit the instantaneous current when two capacitors are connected in parallel (e.g. in Fig. 3c). Seeing that, MOSFET is the preferred switch to realize the proposed converter, due to its resistive behavior when conducting.
With the intention to simplify the analysis, it was assumed the current, independent of the direction, always will be conducted by the MOSFET channel, instead of the body diode. The MOSFET on-resistance is the only parasitic resistance considered in this analysis. However, all resistances in the loop (e.g. equivalent series resistance (ESR) of the capacitors and trace resistance) will assist the capacitor switching.
In order to obtain a steady-state model, it is necessary to extract the equations of each conduction state. First switching state (cf. Fig. 3a) equations are presented in
The new generated topology is called Full-Bridge Hybrid Switched Capacitor (FBHSC) Inverter. A Half-Bridge version was previously presented [30]. The new topology was generated initially by differential connection [31]–[33] between two HSC dc-dc converter [16] (cf. Fig. 2a), which was generated as a bidirectional version of the HSC boost dc-dc converter [34], [35]. The unidirectional dc-dc version can be seen as an integration between a conventional boost dc-dc converter and a voltage multiplier circuit [36].
Some known characteristics of a dc-dc converter are necessary to ensure the generation of a dc-ac converter through differential connection. The HSC dc-dc converter, used as building cell, has all these characteristics, which are:
1) Topology must have voltage source characteristic on the input (i.e. buck-type); 2) Topology must have current source characteristic on the output (i.e. boost-type); 3) Topology must be bidirectional, in order to process both positive and negative current in the output; 4) Topology must have the capability of synthesize an ac output voltage with a dc offset. Fig. 2 presents all steps to generate the proposed topology from the HSC dc-dc converter. The main building cell is presented in Fig. 2a. In Figs. 2b and 2c, two dc-dc converter are connected through a differential connection. Fig. 2d shows the connection between midpoints of each leg, in order to reduce the number of capacitors. Finally, Fig. 2e presented the proposed topology. As previously showed in [37], [38], the same procedure applied can generate a conventional Full- Bridge Inverter from a bidirectional dc-dc buck converter. III. THEORETICAL ANALYSIS OF THE PROPOSED CONVERTER In order to clarify the theoretical analysis, it is necessary to define the proposed topology nomenclature. Capacitors with even index will be called floating capacitors, which are unique to each converter’s leg. The link capacitors have odd index and they are common for all inverter legs. The link capacitor C3 on Fig. 1 is ‘implicit’ because this capacitor is redundant to the theoretical analysis (i.e. its effect can be represented by an equivalent capacitor connected in parallel to C1). Nevertheless, in the prototype all link capacitors must be connected The proposed topology can operate such as common inverters, processing active or reactive power, which will depend on the load angle φ. Initially the load will be assumed as a sinusoidal current source iab, with a function defined by where θ = ω t, and ω is the angular output frequency. Regarding the switches, in each leg all devices with even index have the same modulation signal, same as the devices with odd index. However, each switch must have his own gate driver circuit, as the Neutral Point Clamped Inverter (NPC) or the Floating Capacitor (FC) Inverters, although some alternative topologies of gate-driver circuits could be employed to reduce the number of components [39], [40]. In order to avoid short-circuit in the capacitors, gating signal must be complementary with a dead time between even and odd switches. Then, even switches of leg ‘a’ will be gated by the switching function sa (and 1 − sa to the odd switches), and in the leg ‘b’, even switches will be gated by the switching function …show more content…
Both unipolar and bipolar PWM [41] can be employed. FBHSC modulation scheme is the same as the conventional FB inverter, only with addition of the modulation signal to additional switches.
The proposed topology has only four conduction states, which are presented in Fig. 3.
MOSFET on-resistance Ron is necessary to limit the instantaneous current when two capacitors are connected in parallel (e.g. in Fig. 3c). Seeing that, MOSFET is the preferred switch to realize the proposed converter, due to its resistive behavior when conducting.
With the intention to simplify the analysis, it was assumed the current, independent of the direction, always will be conducted by the MOSFET channel, instead of the body diode. The MOSFET on-resistance is the only parasitic resistance considered in this analysis. However, all resistances in the loop (e.g. equivalent series resistance (ESR) of the capacitors and trace resistance) will assist the capacitor switching.
In order to obtain a steady-state model, it is necessary to extract the equations of each conduction state. First switching state (cf. Fig. 3a) equations are presented in